Control circuits and control methods for over voltage  protection in power suppliers

ABSTRACT

Disclosed include a control circuit adapted for a power controller powered by an operation voltage. When the operation voltage exceeds an over-voltage reference, the power controller stops power conversion provided by a power converter. The control circuit comprises a slope detector detecting a variation slope of the operation voltage. When the variation slope exceeds a drop rate, the slope detector recovers the power conversion. When the power conversion is recovered the power controller compares the operation voltage with the over-voltage reference.

BACKGROUND

The present disclosure relates generally to control circuits and methods adapted for switched mode power supplies, and more particularly to control circuits and methods regarding to over voltage protection in switched mode power supplies.

Power converters are always needed in most electronic devices, to provide adequate power with specific voltage or current that electronic devices require for proper operation. To protect those powering or powered from being damaged by fault operation conditions, most power converters are designed to equip with protection mechanisms, such as over-load protection (OLP), over-temperature protection (OTP), output-short protection (OSP), over-voltage protection (OVP), and the like.

When a feedback loop of a power converter that, to regulate an output voltage, detects the condition of an output voltage is broken, the power converter might mistakenly interpret the output voltage is too low and continue raising its output power, causing the output voltage to rise accordingly. OVP could stop the output voltage from being over high, and prevent those powered by the output voltage from being over stressed.

FIG. 1 illustrates a conventional power converter 8, including flyback topology 10, operation voltage supply 12, and power controller 18. Operation voltage supply 12 provides operation voltage V_(CC) at node VCC, powering power controller 18, which might be in the form of a monolithic integrated circuit.

When a feedback loop that detects the condition of output voltage V_(OUT) at output node OUT is broken, output voltage V_(OUT) might start to increase steadily. Due to the inductive coupling, operation voltage V_(CC) provided by operation voltage supply 12 increases as well. It can be designed that when operation voltage V_(CC) is determined to be over high power controller 18 stops the power conversion provided by power converter 8, such that OVP is achieved.

FIG. 2 exemplifies power controller 18 including oscillator 40, pulse-width modulator 44, OVP control circuit 30, and gate logic 42. Oscillator 40 provides clocks that power controller needs for timing. Pulse-width modulator 44 determines the duty cycle, the ON time of power switch 15 in proportion of a cycle time. OVP control circuit 30 prepares power-good signal S_(PG) to inform gate logic 42 whether operation voltage V_(CC) is good. Gate logic 42 controls power switch 15 via gate node GATE.

FIG. 3A shows operation voltage V_(CC) and power-good signal Sp_(PS) about the time when OVP is triggered due to a broken feedback loop. At the beginning of FIG. 3A, operation voltage V_(CC) is out of regulation and continues to rise. At time point t₁ when operation voltage V_(CC) exceeds over-voltage reference V_(REF-OVP), comparator 34 resets SR flip flop 32, power-good signal S_(PG) is deasserted to be “0” in logic, such that gate logic 42 deems operation voltage V_(CC) to be not good and keeps power switch 15 OFF accordingly, stopping the following power conversion. Thus, OVP is triggered.

As the power conversion is stopped, operation voltage V_(CC) starts to decline because that power controller 18 is alive and consumes the power from operation voltage V_(CC). It might be designed that when operation voltage V_(CC) is lower than reference voltage V_(REF-RSTRT) power conversion is restarted or resumed to raise both output voltage V_(OUT) and operation voltage V_(CC). Nevertheless, power-good signal S_(PG) is kept as being “0” in logic until time point t₂. As shown in FIG. 3A, at time point t₂, operation voltage V_(CC) exceeds reference voltage V_(REF-UV), comparator 36 and single-pulse generator 38 switch power-good signal S_(PG) to be “1” in logic, and gate logic 42 deems operation voltage V_(CC) good from now on. Hold-time T_(HOLD)) represents the time period when power conversion is paused or stopped.

FIG. 3B shows operation voltage V_(CC) and power-good signal S_(PS) about the time when OVP is triggered due to voltage noise temporarily occurring at operation voltage node VCC. As shown in FIG. 3B, operation voltage V_(CC) soars at about time point t₃ because, for some reasons, voltage noise suddenly occurs at operation voltage node VCC. At time point t₃, operation voltage V_(CC) exceeds over-voltage reference V_(REF-OVP), and OVP is triggered. Even though voltage noise subsides soon and operation voltage V_(CC) quickly goes back to its normal value, operation voltage V_(CC) cannot be deemed to be good until operation voltage V_(CC) experiences the similar event sequences shown in FIG. 3A. Namely, operation voltage V_(CC) will decline to reference voltage V_(REF-RSTRT) and then rise to reference voltage V_(REF-UV), as shown in FIG. 3B, such that power-good signal S_(PG) becomes “1” in logic at time point t₄. As shown in FIG. 3B, hold-time T_(HOLD) is considerably long.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 illustrates a conventional power converter;

FIG. 2 exemplifies the power controller in FIG. 1;

FIG. 3A shows operation voltage V_(CC) and power-good signal S_(PS) of FIG. 2 about the time when OVP is triggered due to a broken feedback loop;

FIG. 3B shows operation voltage V_(CC) and power-good signal S_(PS) about the time when OVP is triggered due to voltage noise temporarily occurring at operation voltage node VCC;

FIG. 4 demonstrates an OVP control circuit according to one embodiment of the invention;

FIG. 5A shows operation voltage V_(CC), inverted OVP signal S_(OVP-B), set signal S_(SET), and power-good signal S_(PS) of FIG. 4, about the time when OVP is triggered due to a broken feedback loop; and

FIG. 5B shows operation voltage V_(CC), inverted OVP signal S_(OVP-B), set signal S_(SET), and power-good signal S_(PS) of FIG. 4, about the time when OVP is triggered due to voltage noise temporarily occurring at operation voltage node VCC.

DETAILED DESCRIPTION

FIG. 4 demonstrates OVP control circuit 60, which, in one embodiment of the invention, replaces OVP control circuit 30 in FIG. 2. OVP control circuit 60 has advantage in recovering power conversion soon after voltage noise subsides, or in shortening hold-time T_(HOLD) during which power conversion is paused or stopped.

OVP control circuit 60 has comparator 64, comparator 68, multiplexer 66, low-pass filter 62, and AND gate 70.

Low-pass filter 62 provides filtered voltage V_(CC-LPF) by low-passing operation voltage V_(CC). General circuit analysis can support that low-pass filter 62 limits the speed that filtered voltage V_(CC-LPF) responds to operation voltage V_(CC), and that the difference between filtered voltage V_(CC-LPF) and operation voltage V_(CC) equivalently corresponds to the variation slope of operation voltage V_(CC). For example, the quicker operation voltage V_(CC) drops, the more filtered voltage V_(CC-LPF) exceeds operation voltage V_(CC).

When inverted OVP signal S_(OVP-B) outputted by comparator 64 is “1” in logic, multiplexer 66 couples over-voltage reference V_(REF-OVP) to the non-inverted input of comparator 64. In the opposite, when inverted OVP signal S_(OVP-B) is “0” in logic, multiplexer 66 couples filtered voltage V_(CC-LPF) to the non-inverted input of comparator 64.

Accordingly, if inverted OVP signal S_(OVP-B) is “1”, it implies that operation voltage V_(CC) might not have been too high, and comparator 64 compares operation voltage V_(CC) with over-voltage reference V_(REF-OVP) to check whether operation voltage V_(CC) is too high at this moment. If inverted OVP signal S_(OVP-B) is “0”, it implies that operation voltage V_(CC) has been too high, and comparator 64 compares operation voltage V_(CC) with filtered voltage V_(CC-LPF), equivalently detecting the variation slope of operation voltage V_(CC).

In one embodiment, comparator 64 has a hysteresis effect. When inverted OVP signal S_(OVP-B) is “1”, operation voltage V_(CC) need exceed over-voltage reference V_(REF-OVP) to switch inverted OVP signal S_(OVP-B) to “0”. When inverted OVP signal S_(SVP-B) is “0”, filtered voltage V_(CC-LPF) need exceed operation voltage V_(CC) a predetermined value, 0.5V for example, to switch inverted OVP signal S_(OVP-B) to “1”. This predetermined value, together with low-pass filter 62, corresponds to a certain drop rate. In other words, comparator 64 and low-pass filter 62 together construct a slope detector detecting the voltage variation of operation voltage V_(CC). When the voltage variation of operation voltage V_(CC) exceeds the certain drop rate, meaning operation voltage V_(CC) drops quicker than the certain drop rate, comparator 64 switches inverted OVP signal S_(SVP-B) to “1” in logic.

Comparator 68 compares operation voltage V_(CC) with reference voltage V_(REF-UV). If operation voltage V_(CC) is lower than reference voltage V_(REF-UV), comparator 68 asserts set signal S_(SET) to set comparator 64, such that inverted OVP signal S_(SVP-B) is forced to be “1” in logic, and, as a result, comparator 64 is forced to compare operation voltage V_(CC) with over-voltage reference V_(REF-OVP).

Only when operation voltage V_(CC) has a value between over-voltage reference V_(REF-OVP) and reference voltage _(VREF-UV), it is possible for AND gate 70 to provide asserted power-good signal S_(PG), informing gate logic 42 that operation voltage V_(CC) is good. Otherwise, power-good signal S_(PG) is “0” in logic, meaning the operation voltage V_(CC) is not good.

FIG. 5A shows operation voltage V_(CC), inverted OVP signal S_(SVP-B), set signal S_(SET), and power-good signal S_(PS) of FIG. 4, about the time when OVP is triggered due to a broken feedback loop. At the beginning of FIG. 5A, operation voltage V_(CC) is out of regulation due to a broken feedback loop and continues to rise. Inverted OVP signal S_(OVP-B) is “1” in logic, representing that operation voltage V_(CC) is lower than over-voltage reference V_(REF-OVP).

At time point t₅, operation voltage V_(CC) exceeds over-voltage reference V_(REF-OVP). Comparator 64 switches inverted OVP signal S_(OVP-B) to “0” in logic. Thus power good signal S_(PG) becomes “0” in logic, informing gate logic 42 that operation voltage V_(CC) is not good, such that power switch 15 maintains at an OFF state and power conversion is stopped.

After time point t₅, operation voltage V_(CC) declines mildly. As the voltage variation of operation voltage V_(CC) is relatively small, inverted OVP signal S_(OVP-B) remains as being “0” in logic.

At time point t₆, operation voltage V_(CC) is lower than reference voltage V_(REF-UV) to assert set signal S_(SET). Accordingly, comparator 64 is forced to compare operation voltage V_(CC) with over-voltage reference V_(REF-OVP) and makes inverted OVP signal S_(OVP-B) “1” because operation voltage V_(CC) is lower than over-voltage reference V_(REF-OVP) at this moment. Please note that power good signal S_(PG) is still “0” in logic, and power conversion is still stopped.

When operation voltage V_(CC) is lower than reference voltage V_(REF-RSTRT) gate logic 42 restarts and power conversion is resumed or recovered to raise both output voltage V_(OUT) and operation voltage V_(CC).

At time point t₇ operation voltage V_(CC) exceeds reference voltage V_(REF-UV) and power good signal S_(PG) is switched to be “1” in logic, informing gate logic 42 that operation voltage V_(CC) at present is good.

Power good signal S_(PG) of FIG. 5A is substantially the same with that of FIG. 3A. Accordingly, OVP control circuit 60 of FIG. 4 provides substantially the same OVP function as OVP control circuit 30 of FIG. 2 does.

FIG. 5B shows operation voltage V_(CC), inverted OVP signal S_(SVP-B), set signal S_(SET), and power-good signal S_(PS) of FIG. 4, about the time when OVP is triggered due to voltage noise temporarily occurring at operation voltage node VCC. In contrary to the lengthy hold-time T_(HOLD) in FIG. 3B, hold-time T_(HOLD) in FIG. 5B is relatively short, meaning that power conversion could be resumed to become normal soon after voltage noise subsides. In comparison with the waveform of operation voltage V_(CC) in FIG. 3B, the waveform of operation voltage V_(CC) in FIG. 5B is much flatter, resulting in better voltage regulation.

Operation voltage V_(CC) soars at about time point t₈ because, for some reasons, voltage noise occurs at operation voltage node VCC. At time point t₈, operation voltage V_(CC) exceeds over-voltage reference V_(REF-OVP), both inverted OVP signal S_(OVP-B) and power-good signal S_(PG) becomes “0” in logic, and power conversion is stopped. Hold-time T_(HOLD) starts.

Operation voltage V_(CC) tends to quickly regain its normal value after voltage noise subsides. In the period from time point t₉ to time point t₁₀, operation voltage V_(CC) drops quicker than the certain drop rate defined by comparator 64 and low-pass filter 62, such that inverted OVP signal S_(OVP-B) is switched to “1” in logic, forcing comparator 64 to compare operation voltage V_(CC) with over-voltage reference V_(REF-OVP). Nevertheless, at this moment, operation voltage V_(CC) is still higher than over-voltage reference V_(REF-OVP,) such that inverted OVP signal S_(OVP-B) will be switch back to “0” in logic. As a result, inverted OVP signal S_(OVP-B) continues to toggle between “0” and “1” in logic. So does power-good signal S_(PG), as shown in FIG. 5B. As power conversion is recovered very briefly, very little power, if any, is converted and operation voltage V_(CC) continues to drop and regain its normal value.

After time point t₁₀, operation voltage V_(CC) is surly lower than over-voltage reference V_(REF-OVP). Both inverted OVP signal S_(OVP-B) and power-good signal S_(PG) stay at “1” in logic. Power conversion starts to properly work, claiming the end of hold-time T_(HOLD) in FIG. 5B.

It can be found from FIG. 5B that power-good signal S_(PG) is stabilized to be “1” in logic soon after voltage noise subsides. According, hold-time T_(HOLD) of FIG. 5B is very short. The result shown in FIG. 5B also demonstrates that OVP control circuit 60 of FIG. 4 provides better output voltage regulation than OVP control circuit 30 of FIG. 2 does.

In another embodiment of the invention, a high-pass filter is used to detect the voltage variation of operation voltage V_(CC), and a comparator determines whether the voltage variation exceeds a certain drop rate, to perform the functionality similar with what OVP control circuit 60 of FIG. 4 provides.

While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. 

1. A control method for over-voltage protection adapted for a power converter, comprising: detecting an operation voltage; comparing the operation voltage with an over-voltage reference; stopping power conversion provided by the power converter when the operation voltage exceeds the over-voltage reference; detecting a variation slope of the operation voltage; and recovering the power conversion when the variation slope exceeds a drop rate.
 2. The control method as claimed in claim 1, comprising: providing a comparator; making the comparator detect the variation slope after the operation voltage exceeds the over-voltage reference; and making the comparator compare the operation voltage with the over-voltage reference after the variation slope exceeds the drop rate.
 3. The control method as claimed in claim 2, comprising: comparing the operation voltage with a reference voltage; and making the comparator compare the operation voltage with the over-voltage reference when the operation voltage is lower than the reference voltage.
 4. The control method as claimed in claim 2, wherein the comparator has a hysteresis effect.
 5. The control method as claimed in claim 1, further comprising: low-pass filtering the operation voltage to generate a filtered voltage; comparing the filtered voltage with the operation voltage; recovering the power conversion when the filter voltage is a predetermined value higher than operation voltage.
 6. A control circuit adapted for a power controller powered by an operation voltage, wherein when the operation voltage exceeds an over-voltage reference, the power controller stops power conversion provided by a power converter, the control circuit comprising: a slope detector, for detecting a variation slope of the operation voltage, and, when the variation slope exceeds a drop rate, recovering the power conversion; wherein when the power conversion is recovered the power controller compares the operation voltage with the over-voltage reference.
 7. The control circuit as claimed in claim 6, wherein the slope detector comprises: a low-pass filter for providing a filtered voltage according to the operation voltage; and a first comparator, having a first input coupled to the operation voltage, and a second input coupled to the filtered voltage; wherein when the filter voltage is a predetermined value higher than operation voltage the first comparator renders the power conversion to be recovered.
 8. The control circuit as claimed in claim 7, wherein the slope detection includes: a multiplexer, comprising: a first node coupled to the filtered voltage; a second node coupled to the over-voltage reference; a select node coupled to an output node of the first comparator; and a multiplexer output coupled to the second input of the first comparator.
 9. The control circuit as claimed in claim 7, wherein the first comparator has a hysteresis effect.
 10. The control circuit as claimed in claim 8, comprising: a second comparator, for comparing the operation voltage with a reference voltage; wherein when the operation voltage is lower than the reference voltage the second comparator makes the multiplexer select the over-voltage reference to be output at the multiplexer output.
 11. The control circuit as claimed in claim 7, further comprising: a second comparator for comparing the operation voltage with a reference voltage; wherein when the operation voltage is lower than the reference voltage the second comparator resets the first comparator. 